Improved Layout Style on Diode- Trigger SCR for Low-C ESD Protection

Electrostatic discharge (ESD) protection design for radio-frequency integrated circuits (RFICs) and high-speed I/O circuits is a challenge due to the parasitic capacitance generated from ESD devices, which significantly degrades circuit performance under high-frequency/high-speed operation. Striking a balance between effective ESD protection and maintaining high-frequency/high-speed circuit performance is strongly requested by IC industry. In this work, an improved layout is proposed to significantly reduce the parasitic capacitance of the diode-trigger silicon-controlled rectifier (DTSCR) device while maintaining high ESD robustness. The DTSCR with improved layout has been verified in a 28-nm fully-silicide CMOS process with the experimental result of high ESD robustness per unit capacitance, which is suitable for on-chip ESD protection design with low-C requirement.