Refined High Resistance Baking Approaches for Optimal Interconnect Reliability

Advancements in semiconductor technology have significantly reduced Stress Migration (SM) failure rates (F/R), making it challenging to determine critical stressand thermal diffusion parameters in SM model. This paper tackles these challenges through the design of extremely wide metal patterns. We demonstrate that the Arrhenius diffusion term can be utilized for SM modeling to predict product usage lifetime in optimal interconnect technology, with Ea=leV and a negligible stress effect N=1. Conversely, the latent defects can also be detected by baking at temperatures above the SM peak of 200°C, in accordance with the Arrhenius equation. This work refines the high-R baking approach and propose that the Arrhenius diffusion model can address both intrinsic SM and defective high-R to enhance BEOL reliability.