Influence of Process Integration on pBTI Degradation in Analog SOI nMOSFETs

This paper investigates positive Bias Temperature Instability (pBTI) degradation in nitrided SiO2 gate oxide of Silicon-On-Insulator (SOI) nMOS transistors for analog applications. PBTI drifts are measured under various gate voltage stresses <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{GStress})$</tex> and maximum stress durations <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(t_{Stress})$</tex>: They revealed two distinct trap populations modeled using the Capture Emission Time (CET) mapping approach. The first trap population resides within the SiO2 gate oxide above the silicon conduction band minimum (Ec) and displays a recoverable behavior. In contrast, the second population lies at the Si/SiO2 interface and exhibits an irreversible behavior. The latter was studied using capacitance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C(V_G)$</tex> and conductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$G(V_G)$</tex> measurements that were simulated to estimate the interface trap density <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(D_{it})$</tex> after various stress conditions. The result reveals a characteristic Gaussian profile of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$D_{it}$</tex> centered at 0.28eV below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_C$</tex> likely associated with nitrogen-induced defects. Additionally, the study demonstrates a significant reduction in recoverable traps when comparing two manufacturing processes, offering valuable insights to enhance pBTI and Hot Carrier Injection (HCI) reliability of nitrided SiO2 gate oxide.