CoWoS Package Reliability Risk Assessment & Mitigation from Mechanical Perspectives

The increasing demand for computing power in generative AI applications has prompted the use of advanced packaging technologies like 2.5D and 3D ICs, which enable vertical component stacking. Technologies such as chip-on-wafer-on-substrate (CoWoS) integrate multiple chips, including logic systems-on-chip and high-bandwidth memory, within a single package. Heterogeneous material integration and large package sizes creates development challenges, necessitating material and mechanical characterization to provide crucial insights. Tests like double cantilever and nano-indentation provide critical data on interface robustness and stress resistance, aiding in reliability risk assessment and guiding material selections to ensure long-term operation performance at fields of application.