Investigation and Mitigation of Transistor Induced Reliability Issues in 40NM RRAM Array

This study systematically investigates operational reliability degradation in 1-transistor-1-resistive memory (1T1R) arrays implemented in a commercial 40nm CMOS technology node. While prior research has predominantly focused on resistive switching element characteristics, we quantitatively examine the previously underexplored device degradation mechanisms in access transistors under programming overstress conditions. Through comprehensive characterization of both selected and half-selected cells in 1T1R arrays, we identify that array-level reliability concerns are closely linked to the array size, and propose an operation optimization scheme to mitigate these reliability issues.