Optimized CDM-ESD Protection for 100+ Gbps Wireline IO in 16-nm CMOS

This work presents an ESD solution for high-speed serial IO pins, in which a STI-poly-bounded silicon-controlled rectifier (SCR) is integrated into an impedance matching circuit. The proposed all-pass secondary protection network provides excellent voltage clamping under CDM-like conditions, resulting in a peak voltage of just 2 V in response to 5-A 1-ns VFTLP current injection. Integrated with a T-coil circuit, the network achieves a bandwidth above 40 GHz, as well as broadband impedance matching.