HTGB and DGS Reliability Assessment of e-mode GaN-HEMTs with Ferroelectric Gate Stack

This study investigates the reliability of enhancement-mode GaN-HEMTs with ferroelectric gate dielectric stack under High Temperature Gate Bias (HTGB) and Dynamic Gate Stress (DGS) conditions. The gate Time To Failure (TTF) is analyzed across varying gate voltages (VG), temperatures (T), switching frequencies (fS) and duty cycles (D). Under static HTGB stress, wear-out mechanisms leading to gate breakdown show no dependence on the gate's perimeter or area, suggesting that failure is localized to specific high-stress regions, such as gate corners. Lifetime projections under HTGB at 150°C estimate a maximum VG of~ 9.6 V for a 10-year lifetime. In contrast, under pulsed DGS conditions, a higher VG is achievable, possibly due to charge recovery during OFF-states. Finally, the DGS analysis further reveal that D plays a fundamental role in mitigating damage, while fS has negligible impact.