New Burnout Failure at the Chip Edge: Analysis and Preventive Design by a Novel Experimental Approach

To meet the growing demand for high bit density, memory devices have adopted 3-D stacking technology. In many applications, vertical packaging height is constrained, so as the stacked memory cells within the chip increase in thickness, the silicon substrate thickness must decrease. When a thinner substrate with modified chip warpage is combined with a triboelectric charging during the packaging process, it leads to a newly observed burnout failure at the chip edge, which manifests as standby failures in DC tests after assembly. This failure mode causes significant yield issues in multi-die packages and also threatens product reliability. In this study, we identify the root cause through failure analysis and isolate the dominant factors through electrical and thermal-mechanical analyses. Finally, we propose a process design to mitigate these burnout failures.