Characterization and Modeling of Fully Depleted SOI Varactor With Independently Controlled Front- and Back-Gates for RF Applications

In this work, we have explored the influence of back-gate voltage on the terminal characteristics of fully depleted silicon-on-insulator (FDSOI) varactors, which are crucial for RF applications. We characterized 28-nm FDSOI varactors in terms of both ac and RF performance. Experimental results highlight the significant effect of back-gate voltage on device behavior, revealing transitions between different operational modes, such as accumulation, depletion, and inversion. Unique features observed in the ultrathin body and box (UTBB) FDSOI varactor, including a hump in gate capacitance, distinct series resistance trends, and quality factor variations, have been extensively analyzed over a wide range of back-gate biases, spanning from strongly negative to strongly positive. In addition, a phenomenological model based on the physical parameters of the device is introduced and has been successfully validated with the industry hardware data, showing excellent correlation. The model accurately predicts key performance metrics, including capacitance and quality factors, over a broad bias and frequency range. To extend the utility of the model for accumulation mode varactors, a model of series resistance is proposed and validated with TCAD simulation results. This model, implemented in Verilog-A, can be readily integrated into standard circuit simulators.