Improved Memory Window and Retention of Silicon Channel Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> FeFET by Using SiO<sub>2</sub>/HfO<sub>2</sub>/SiO<sub>2</sub> Gate Side Interlayer
We demonstrate a Si-channel Hf<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf>.<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</inf>Zr<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf>.<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>FeFET that achieves a record-high memory window (MW) of up to 19.4 V, together with improved data retention. This advancement is realized by inserting the SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>/HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>/SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>gate interlayer between the metal gate and the ferroelectric Hf<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf>.<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</inf>Zr<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf>.<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>layer. The gate interlayer effectively retains the charges injected from the metal gate. The influence of SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>thickness on the reliability was investigated. Although thicker SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>layer enhance the memory window, its endurance is poor. The data retention improves with increasing SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>layer thickness. Furthermore, the charge trapping behaviors of gate-injected electrons and holes are asymmetric. This work provides new insights into the gate-injected charges and data retention in the FeFETs with gate interlayer.
Authors
- Tianchun Ye (ORCID: https://orcid.org/0000-0002-2384-9037)
- Runhao Han (ORCID: https://orcid.org/0000-0001-9923-5456)
- Saifei Dai (ORCID: https://orcid.org/0000-0001-7433-9347)
- Xiaoqing Sun (ORCID: https://orcid.org/0000-0002-9497-7634)
- Junshuai Chai (ORCID: https://orcid.org/0000-0001-5569-5071)
- Mingkai Bai (ORCID: https://orcid.org/0000-0001-9808-1694)
- Xiaolei Wang
- Xianzhou Shao
- Jia Yang (ORCID: https://orcid.org/0000-0002-1438-1698)
- Yajing Ding (ORCID: https://orcid.org/0009-0009-9607-7371)
- Hao Xu
- Tao Hu (ORCID: https://orcid.org/0009-0004-3265-6095)
- Wenwu Wang
Institutions
- Chinese Academy of Sciences (CN)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10983393
- Citations
- 2
- Primary Topic
- Ferroelectric and Negative Capacitance Devices
- Type
- article
- Field-Weighted Citation Impact
- 1.46