Hot Carrier Degradation and performance boost on Si Channel nFET Gate-All-Around Nanosheet Devices

In this paper, hot carrier reliability on ultra-scaled gate length (Lg) substrate-isolated Gate-All-Around (GAA) nanosheet (NS) transistors is studied for the first time. Detailed characterization of hot carrier degradation (HCD) under Mid-V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> and High-Vg is performed and investigated. HCD impact from interface and oxide traps is decoupled, which is critical for improving oxide quality, reliability and interface/junction optimization for a variety of circuit applications. Robust hot carrier injection (HCI) End-of-Life (EOL) is achieved under both stress condition after self-heating correction (SHC). Performance boost and reliability are critical to technology development. Inner spacer (IS), as a unique module for GAA NS architecture, generates more challenges to performance boost, and its sensitivity to HCD has never been evaluated on 3nm technology and beyond. For IS thickness (THK) reduction and junction optimization, two of the key elements for performance improvement [16], design of experiments (DOE)s demonstrates a path to achieve performance step up. Thorough study of HCD is performed on GAA NS transistors with IS THK reduction and junction DOEs, followed by comparison with a reference result (Ref.). The IS THK reduction DOE shows higher HCD sensitivity than conventional spacer THK from FinFET [17]. Additional traps from thinner IS suggest that material quality improvement is required for performance boost with IS THK engineering. GAA NS transistors with the junction DOE show performance improvement with mitigated HCD, suggesting more overlap and abrupt junctions give HCI EOL margin for technology qualification with additional performance boost.