Introduction to Voltage-Ramping Wafer Level Electromigration Method and Current Exponent Correction Factor for Co-Capping Metal Lines
This paper presents a novel voltage-ramping (V-ramp) wafer-level electromigration (EM) testing method aimed at reducing testing time. The EM behavior of copper (Cu) metal lines with both CuMn seed layer and cobalt (Co) capping layer is investigated. Results demonstrate two distinct behaviors. Cu metal lines with CuMn seed layer exhibit a strong correlation with conventional package EM results, while those with Co-capping do not. To enhance accuracy in determining time-to-failure (TTF), we propose a new current exponent correction factor, which enables more precise TTF calculations and improves correlation. This research introduces an efficient EM testing approach and advances the understanding of Cu metal line behavior in the presence of a Co capping layer.
Authors
- Myungsoo Yeo
- Hyunjun Choi (ORCID: https://orcid.org/0000-0002-4507-5052)
- Taiki Uemura
- Doosup Shin (ORCID: https://orcid.org/0000-0003-4960-5732)
- Jong‐Ho Lee (ORCID: https://orcid.org/0000-0003-4481-6258)
- Miji Lee (ORCID: https://orcid.org/0000-0002-8063-5326)
- Shinyoung Chung
- Joosung Kim
Institutions
- Samsung (South Korea) (KR)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10982900
- Primary Topic
- Copper Interconnects and Reliability
- Type
- article
- Field-Weighted Citation Impact
- 0.00