Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection

The conventional HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>-based n-type ferroelectric field-effect transistors (nFeFETs) suffer from read-after-write delay (RAWD), caused by electron detrapping at the channel interface after positive write pulses. In this work, we propose a metal-insulator-ferro-insulator-silicon (MIFIS) nFeFET structure incorporating a SiN<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> charge trapping layer between the ferroelectric and gate metal to introduce gate-side injection (GSI) of positive charges under positive write pulses. This mechanism reinforces the remnant polarization and the interlayer electric field to prevent channel-side electron detrapping, leading to enhanced memory window and immediate read-after-write capability. Experimental results demonstrate that the MIFIS FeFETs with 5nn-thick SiN<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> charge trapping layer exhibit significantly larger MW of 7.9V and negligible low-threshold voltage (LVT) shifts between µs and 1s after write operation delay compared to conventional metal-ferro-insulator-silicon (MFIS) FeFETs. Furthermore, TCAD simulations on MIFIS nFeFETs with 5nm SiN<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> and 10nm ferroelectric layer reveal the underlying mechanisms, showing that the additional injected charges strengthen polarization and create an energy barrier against electron detrapping. These findings highlight the potential of MIFIS structures in overcoming RAWD issue, enabling faster operation in FeFET-based memory systems.