Reliability Performances Tuning in Ge-rich GeSbTe Phase-Change Memory Thanks to Multilayered Ge//GeSbTe Stacks

This study investigates the engineering by Mul-ti-Layer (ML) approach of off-stoichiometric Ge-rich GeSbTe alloys to improve performance and reduce electrical variability while maintaining high-temperature stability of phase-change memory (PCM) devices integrated on 130 nm bulk and 28 nm FDSOI CMOS technologies. We show that tuning the Ge layer thickness and Nitrogen content of Ge(N)//GeSbTe ML stacks improves layer stability at high temperature, the resistance win-dow, and the SET reliability. Thicker Ge layers enhance the ML integrity, while higher N content improves the resistance window but compromises SET stability at high temperatures. Ultimately, ML design offers an effective method to control intermixing and high temperature stability, while also enabling Multi-level cell capability. These results demonstrate the high potential of Ge//GeSbTe MLs to target ultimate scaling of off-stoichiometric alloys featuring stability at high temperature in advanced next generation technology nodes.