The Importance of Gate Length Choice on NBTI Qualification in GAA-SNS FETs Under Normal and Overclocking Conditions

The fully physical Bias Temperature Instability (BTI) Analysis Tool (BAT) is used to analyze ultra-fast (10µS delay) measured Negative Bias Temperature Instability (NBTI) stress and recovery kinetics in Gate All Around Stacked Nano-Sheet (GAA-SNS) Field Effect Transistors (FETs) featuring different gate length (L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf>). The relative contributions of trap generation (at the channel/gate insulator interface and inside gate insulator) and trapping (inside gate insulator) subcomponents are isolated using shorter-time stress conditions at different stress gate bias (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf>) and temperature (T). The isolated subcomponents are then leveraged to extrapolate NBTI to End-of-Life (EOL) at normal and overclocking scenarios. L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> scaling is shown to reduce NBTI along with its underlying subcomponents, highlighting the need for selecting optimal L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> for effective gate stack optimization.