Well-Charging Damage to Capacitors Connected Between VDD and VSS in a Single Power Domain
In this paper, we report on the charging damage observed in capacitors situated within a single Deep N-Well (DNW) during integrated circuit processing. These capacitors, connected between VDD and VSS within a single power domain, accumulate charge from backend metal/via antennas during plasma etching. Our study delves into the behavior and mechanisms underlying this charging damage, utilizing extensive test-patterns. Based on the results and the identified mechanisms, we propose the layout and design guidelines to mitigate such damage.
Authors
- Ryan Lu (ORCID: https://orcid.org/0000-0003-0922-3342)
- Yilun Chen (ORCID: https://orcid.org/0000-0002-9134-9368)
- Kuo-Ji Chen
- Ming-Hsiang Song
- Chien‐Jen Wang
- Chun-Wei Yao (ORCID: https://orcid.org/0000-0002-9032-9592)
- Tsung-Yuan Chen (ORCID: https://orcid.org/0000-0002-1155-1372)
- Yi-Ching Chen (ORCID: https://orcid.org/0000-0002-8862-7881)
- Kejun Xia (ORCID: https://orcid.org/0000-0002-4210-345X)
- Te-Liang Li
- Hsin Chu (ORCID: https://orcid.org/0000-0002-8155-8860)
- Chia-Lin Hsu
- Yu-Lin Chu (ORCID: https://orcid.org/0009-0000-7250-7976)
- Ray Huang
- Hung-Yi Kuo
- Steven S.S. Poon
- Yu-Ti Su
Institutions
- Quality and Reliability (Greece) (GR)
- Educational Service District 123 (US)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10982926
- Primary Topic
- Non-Destructive Testing Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00