Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices

Performance enhancement of DRAM memory will eventually require a switch of periphery transistors from planar to finFET configuration. In this work we explore gate-stack options for thick oxide (high-voltage) transistors of DRAM periphery compatible with finFET architecture. We investigate different thick oxide interface layer processes, gate stacks and processing steps and their impact on NBTI, V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</inf> and EOT. A defect-centered analysis enables the correlated interpretation of the trends of these electrical metrics.