Fast CV MSM Technique for Comprehensive Analysis of Bulk Trapping in Low-K Carbon-Doped Dielectrics
This study employs a fast and accurate capacitance-voltage (CV) measurement technique to characterize the trapping behavior of low-k dielectrics, using large MOS capacitors with carbon-doped silicon oxide insulators processed through various thermal treatments. The fast CV single ramp method enables accurate extraction of capacitance characteristics while minimizing bulk trapping effects during measurement. Measurement Stress Measurement technique reveals the time-dependent behavior of electron and hole trapping in different process splits allowing for a deeper understanding of trap dynamics and the energy distribution of traps within the dielectric.
Authors
- V. Lapras (ORCID: https://orcid.org/0009-0000-1746-8716)
- B. Garros
- M.-C. Cyrille
- T. Mota Frutuoso (ORCID: https://orcid.org/0000-0001-7067-4893)
- Alan M. Bond (ORCID: https://orcid.org/0000-0002-1113-5205)
- W. Vandendaele
- Fabien Bringuier
- C. Fenouillet-Béranger
Institutions
- Commissariat à l'Énergie Atomique et aux Énergies Alternatives (FR)
- Laboratoire d'Électronique des Technologies de l'Information (FR)
- Université Grenoble Alpes (FR)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10983765
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.73