Power-Aware Mitigation of Logic Soft Error Rates at the 3-nm Bulk FinFET Node
Mitigation of logic soft errors results in heavy performance penalties. Power-aware mitigation allows for the optimization of power, speed, and soft-error rates. Results from heavy-ion irradiations are used to show the effectiveness of this approach.
Authors
- Nicholas J. Pieper (ORCID: https://orcid.org/0000-0003-4968-7029)
- Dennis R. Ball (ORCID: https://orcid.org/0000-0003-0411-1835)
- Yoni Xiong (ORCID: https://orcid.org/0000-0002-3635-7429)
- B. L. Bhuva (ORCID: https://orcid.org/0000-0002-2171-100X)
- Jenna B. Kronenberg (ORCID: https://orcid.org/0009-0009-4632-6704)
Institutions
- Vanderbilt University (US)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10983458
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00