ReHIT: Reconfigurable High-Radix Iterative-Taylor Architecture for Ultraprecise Logarithm/Exponential Functions in FPGA-Based Softmax Accelerators
The softmax function, as a pivotal component in neural network accelerators, imposes stringent demands on the precision-efficiency tradeoff for logarithmic and exponential computations. This article presents reconfigurable high-radix iterative-Taylor (ReHIT) architecture, a novel hardware framework that synergistically integrates high-radix iterative normalization with optimized Taylor expansion to achieve subunit-in-the-last-place (ULP) precision in floating-point transcendental functions. Our key innovation lies in the hierarchical pretreatment mechanism where high-radix iterations (radix-256/512) systematically decompose input operands into normalized subdomains, enabling subsequent quadratic Taylor approximations with guaranteed convergence. This codesign methodology reduces polynomial orders by 33% compared to conventional approaches while eliminating resource-intensive division operations through shift-and-add transformations. The implemented ReHIT-logarithm (ReHIT-L) and ReHIT-exponential (ReHIT-E) modules demonstrate configurable precision scaling from half to double precision (FP16/32/64), validated through exhaustive error analysis over 1 000 000 random test vectors with worst case errors bounded at 0.78 ULP. Field-programmable gate array (FPGA) implementations on Arria 10/Virtex-7 platforms can achieve up to 13.8% logic resources reduction and 32.3% latency improvement over state-of-the-art designs, with post-synthesis results in Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm showing up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.34\times $</tex-math> </inline-formula> giga operations per second (GOPS)/W energy efficiency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.97\times $</tex-math> </inline-formula> GOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area efficiency for softmax acceleration. The reconfigurable pipeline of the architecture permits dynamic precision/throughput adaptation, particularly beneficial for quantized neural networks requiring FP16–FP32 hybrid precision.
Authors
- Xianglong Wang (ORCID: https://orcid.org/0000-0003-1086-5158)
- Fengwei An (ORCID: https://orcid.org/0000-0002-7554-7938)
- Lei Chen (ORCID: https://orcid.org/0000-0002-8257-5806)
- Yangyi Zhang (ORCID: https://orcid.org/0009-0009-8348-6424)
Institutions
- Southern University of Science and Technology (CN)
Publication Details
- Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2025-05-15
- DOI
- https://doi.org/10.1109/tvlsi.2025.3566433
- Citations
- 1
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 2.27
Funders
- Chuzhou Science and Technology Program
- Shenzhen Science and Technology Innovation Program