DCLL: Depth-coupling based approach on logic locking

Logic locking is a technique designed to safeguard integrated circuit netlists from security threats. However, recent advancements in machine learning-based structural attacks have significantly challenged existing logic locking methods. Moreover, current defenses against these structural attacks often diminish the resilience of logic locking against Boolean satisfiability-based attacks (SAT attacks). To address this limitation, this paper presents the Depth-Coupling Logic Locking (DCLL) technique. DCLL utilizes a key to control a multiplexer and an XOR gate, establishing a robust interconnection at the functional level. By incorporating subgraph replacement, DCLL enhances both the locking mechanism and its resistance to SAT attacks. Experimental results reveal that DCLL achieves an exponential increase in SAT attack resistance while maintaining robustness against machine learning-based removal attacks. Furthermore, DCLL provides a balanced defense against oracle-guided (OG) and oracle-less (OL) attacks. For circuits with one million gates, DCLL incurs minimal overheads of 0.37% in area and 0.40% in power, positioning it as an efficient and effective solution for enhancing the security of logic locking techniques.