A High Timing Resolution and Data Rate Pulse Generator for Automatic Test Equipment Applications

Arbitrary waveform generators (AWG) and algorithmic pattern generators (ALPG) typically adopt the functionality achieved by combining multiple pulse generators (PGs). If the data rate and timing resolution of a single PG can be efficiently improved, using multiple PGs will result in a multiplicative increase in performance. The 2Gbps PG with a timing resolution of 1.97 ps has been designed. The proposed PG uses an edge combiner (EC) and a phase-locked loop (PLL). The EC provides a programmable waveform with a timing interval of 1.97 ps and employs a counter scheme and an MOS varactor to define the operational data rate range and timing resolution. To combine the period window with the PLL output, the EC uses the WIN controller, which incorporates a count-up counter, to enable a wide operational range. WIN controller operates with only one window to simplify its sampled circuit. The timing resolution of the coarse-tuning stage (CTS) was determined from the PLL period. The fine-tuning stage (FTS) introduces an auto-calibration circuit to achieve high-timing resolution. This auto-calibration technique ensures consistent timing resolution and tuning range under process, voltage, and temperature variations (PVT) variations. The digital-type calibration scheme can achieve low power consumption. In addition, a replica delay line scheme is proposed to compensate for the tuning range of the FTS, thereby enabling the PG to maintain high-accuracy waveforms under PVT variations. For the high timing resolution, the proposed MOS varactor with a digital-to-analog converter, DACs, (MOS-DAC) in FTS is adopted to achieve multi-bit control for timing resolution, thereby reducing the number of stages in the delay line and minimizing power consumption. The test chip was fabricated using a 90-nm CMOS process, with a core area of 215 × 367 μm2 and power consumption of less than 10.55 mW. The data rate range of the PG spanned 977.6 kbps to 2 Gbps, and the timing resolution and average accuracy were 1.97 ps and ±1.18 LSB (Least Significant Bit), respectively. Therefore, a well-designed PG is highly beneficial for automatic test equipment (ATE) systems.

Authors

Institutions

Publication Details

Journal
IEEE Transactions on Instrumentation and Measurement
Published
2025-01-01
DOI
https://doi.org/10.1109/tim.2025.3569883
Primary Topic
Engineering and Test Systems
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

A High Timing Resolution and Data Rate Pulse Generator for Automatic Test Equipment Applications

Jen‐Chieh Liu, Chengxuan Wu, Chi-Hua Chen
IEEE Transactions on Instrumentation and Measurement
Engineering and Test Systems
article

A High Timing Resolution and Data Rate Pulse Generator for Automatic Test Equipment Applications

Jen‐Chieh Liu, Chengxuan Wu, Chi-Hua Chen
article en

Abstract

Arbitrary waveform generators (AWG) and algorithmic pattern generators (ALPG) typically adopt the functionality achieved by combining multiple pulse generators (PGs). If the data rate and timing resolution of a single PG can be efficiently improved, using multiple PGs will result in a multiplicative increase in performance. The 2Gbps PG with a timing resolution of 1.97 ps has been designed. The proposed PG uses an edge combiner (EC) and a phase-locked loop (PLL). The EC provides a programmable waveform with a timing interval of 1.97 ps and employs a counter scheme and an MOS varactor to define the operational data rate range and timing resolution. To combine the period window with the PLL output, the EC uses the WIN controller, which incorporates a count-up counter, to enable a wide operational range. WIN controller operates with only one window to simplify its sampled circuit. The timing resolution of the coarse-tuning stage (CTS) was determined from the PLL period. The fine-tuning stage (FTS) introduces an auto-calibration circuit to achieve high-timing resolution. This auto-calibration technique ensures consistent timing resolution and tuning range under process, voltage, and temperature variations (PVT) variations. The digital-type calibration scheme can achieve low power consumption. In addition, a replica delay line scheme is proposed to compensate for the tuning range of the FTS, thereby enabling the PG to maintain high-accuracy waveforms under PVT variations. For the high timing resolution, the proposed MOS varactor with a digital-to-analog converter, DACs, (MOS-DAC) in FTS is adopted to achieve multi-bit control for timing resolution, thereby reducing the number of stages in the delay line and minimizing power consumption. The test chip was fabricated using a 90-nm CMOS process, with a core area of 215 × 367 μm2 and power consumption of less than 10.55 mW. The data rate range of the PG spanned 977.6 kbps to 2 Gbps, and the timing resolution and average accuracy were 1.97 ps and ±1.18 LSB (Least Significant Bit), respectively. Therefore, a well-designed PG is highly beneficial for automatic test equipment (ATE) systems.

IEEE Transactions on Instrumentation and MeasurementVol. 74
National United University (TW)
Affordable and clean energy
Openalex Percentile: Top 89%
Engineering and Test Systems
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.