Impact of Saturated Spontaneous Polarization on the Memory Window and Endurance of Hafnium-Based Si Channel FeFET

In this work, we investigate the impact of saturated spontaneous polarization (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>S</i></sub>) of the ferroelectric layer on the memory window (MW) and the endurance of hafnium-based Si channel ferroelectric field-effect transistors (FeFETs). We tune <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>S</i></sub> within the range of 3.85–18.31 μC/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup> by varying the proportions of hafnium (Hf) and zirconium (Zr). The results show that the MW and endurance of the FeFETs initially increase and then decrease with the decrease of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>S</i></sub>. We find that the lower limit of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>S</i></sub> is about 8 μC/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup> due to the rapid increase in trapped charge (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>t</i></sub>). To clarify the underlying mechanism of the rise in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>t</i></sub>, we model the threshold voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub>) by considering charge trapping in the FeFET gate-stack. The simulation results show that defect energy levels exist near the Fermi level of the Si substrate under flat band conditions and are capable of capturing electrons and holes during write operation, which deteriorates the MW in FeFETs even at smaller <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>S</i></sub>. Furthermore, the generation of deep energy level defects contributes to a greater charge trapping, which degrades the endurance. Our findings highlight that the passivation of deep-level defects is a crucial strategy for improving the endurance of FeFETs.