An Energy-Efficient Four-Channel Interface ASIC for IRFPAs With Optimized Resistor-Sharing Technique Achieving 88.1-dB SNDR

This article presents a four-channel interface application-specific integrated circuit (ASIC) for infrared focal plane arrays (IRFPAs), where each channel integrates a programmable gain amplifier (PGA) with wide-range input common-mode adjustment capability and a 16-bit hybrid analog-to-digital converter (ADC) with resistor-sharing technique (RST). The flash stage of the ADC performs 5-bit most significant bits (MSBs) conversion, whose results are transferred to thermometer-coded capacitor array in the successive approximation register (SAR) stage, ensuring high linearity while maintaining conversion speed. This hybrid architecture of the ADC uses the RST by sharing the resistor ladder between the flash and SAR stages, reducing power consumption. The interface ASIC fabricated in the 180-nm CMOS technology achieves an input common-mode adjustment range of 0.169–3.269V. Operating at 2 MS/s with a 3.3-V supply, it achieves an 88.1-dB signal-to-noise-and-distortion ratio (SNDR) and consumes 13.97 mW/channel. The Schreier figure-of-merit (FoM) of the ADC reaches 171.2 dB/channel. Measured differential and integral nonlinearity (DNL/INL) are −0.38/+0.49 least significant bits (LSBs) and −2.2/+1.4 LSB, respectively.