Physical insights into optimization of dual metal gate junctionless tree-shaped FETs at sub-5 nm technology node: device to circuit approach

Abstract The study marks the first comprehensive exploration of sub-5 nm technology node Dual Metal Gate Junctionless (DMG-JL) TreeFET employing a multi-faceted lens encompassing Work Function Modulation (ΔW), Metal Gate Length Ratio (MGLR), Temperature, and Spacer dielectric materials. Using well calibrated TCAD simulation setup, the significant insights into digital, analog/RF performance characteristics is presented and feasible fabrication process flow is also proposed. Across ΔW variations from 0.3 eV to 0.9 eV, lower ΔW yields superior I OFF (∼10 −15 A), I ON /I OFF ratio (∼10 10 ), and SS (∼73 mV dec −1 ), alongside enhanced analog/RF attributes like A V , f T , and f MAX . Further, to observe the performance enhancement, the MGLR is varied in five specific configurations where S and D denotes source and drain: (i) L tD = 4 nm, L tS = 12 nm (1:3), (ii) L tD = 6 nm, L tS = 10 nm (1:1.6), (iii) L tD = 8 nm, L tS = 8 nm (1:1), (iv) L tS = 4 nm L tD = 12 nm (1:3), (v) L tS = 6 nm L tD = 10 nm (1:1.6), it is found that configurations (i), (ii) gives better digital performance with I ON /I OFF ratio ∼10 11 while the configurations (iii), (v) gives better analog/RF performance with A V ∼47 dB. Temperature variation (250 K–450 K) studies highlight improved metrics at lower temperatures (250 K), showcasing cryogenic application potential. Moreover, opting a high-k spacer material is suitable for digital, analog applications while low-k spacers suit RF applications. Comparing with SMG, the DMG-JL TreeFETs exhibited heightened gain for CS amplifiers, promising tailored low-power designs for next-generation ultra-scaled digital, analog/RF ICs.