Optimized design of digital comparator using QCA

Abstract This study introduces a single-bit comparator circuit designed using QCA. The proposed design surpasses existing designs comprehensively in every aspect. This study introduces an innovative approach to enhancing the robustness of a QCA-based single-bit comparator through a newly developed design. This approach contributes to its low complexity and potentially reduced energy consumption. In the comparison with the literature, the proposed design comprises of only 19 cells and best clock latency is observed with a value of 0.25 clock cycles. Fault tolerance analysis is performed on the comparator to identify potential vulnerabilities and optimize the fabrication process. To evaluate the performance of this comparator, software tools such as QCA Designer-E and QCA Pro are used to estimate its overall energy dissipation. The detailed findings are presented within the broader context of the paper.