Optimization of Power Consumption and Delay Balance Based on Sizing

Because of the development of chip manufacturing, the energy consumption of circuit is gradually increasing. Thus, it brings more demand to the circuit design. This paper presents three methods of sizing to reduce the energy consumption of the circuit, so as to achieve a optimization between delay and energy. To illustrate it, this paper first designs a high-performance 4-bit absolute-value detector and then calculate its minimum delay and the energy consumption with minimal delay. After that, this paper Consider changing gate sizing and supply voltage to achieve minimum energy while delay is less than 1.5 times minimum delay. At the meantime, the delay of critical path and the energy consumption of whole circuit are properly analyzed and modeled. Based on the model, it is easier to optimize energy and delay. After the design and optimization, it turns out that sizing is practical for reducing energy of circuit. Combining with sizing and adjusting supply voltage, the energy consumption reduces about fifty-eight percent than before. Moreover, this paper proposes three general ways of sizing to reduce energy consumption.