Optimization of 4-bit Absolute-Value Detectors in CMOS: Design Strategies for Reduced Delay and Power Consumption

In the evolving fields of biomedical signal processing and computer processing technology, absolute value comparators play a crucial role in data manipulation and decision-making. However, existing designs often face issues of significant delay and energy consumption. This study introduces a novel static-logic 4-bit Absolute-value Detector, utilizing Pass-Transistor Logic (PTL) in CMOS technology, aimed at minimizing propagation delay worst-case and total energy consuming from the supply voltage. By making critical adjustments to the critical path delay and gate sizing, the AVD achieved an impressive 40% reduction in total energy consumption, although the critical path delay increased to 102.86ps. This design represents a significant advancement over traditional comparator-based AVDs, featuring a shorter critical path and avoiding high-fan-in gates. Despite its limitations, such as the excessive use of logic gates, future improvements may involve integrating a mirror adder at critical points. This study contributes to ongoing efforts to optimize absolute value detectors for neural signal acquisition systems, enhancing efficiency and reliability in computational neuroscience.