An Improved 4-bit Absolute Value Detector Based on Energy Supply Voltage Control

The 4-bit absolute value detector (AVD) is a simple and popular circuit design. This article enriches the functionalities of several logic gates utilizing CMOS technology and improves the circuit by controlling the supply voltage (VDD) in order to increase its performance in terms of both delay and power consumption. Subsequently, the circuit was redesigned using real-world CMOS technology and developed using logical expressions. Following the optimization of the design, the logic effort theory is applied in this article to theoretically analyze the circuit's shortest delay and ascertain the precise gate size of each logic component. In order to adjust the delay and power consumption of the circuit to a more appropriate state, this article optimizes power consumption by increasing a certain delay and changing the way the power supply voltage is supplied. The attempt in this article will contribute to the application of this solution in more circuit designs in the future.