On the Phase-Matching Design Condition of Distributed Amplifier Based Frequency Multiplier

Single- and dual-fed distributed amplifiers based frequency multipliers are analysed for the phase-matching design condition. Based on the nonlinear circuit analysis, phase-matching design conditions are found such that the transistors have an equal contribution to the total output power and also the total output power level on the desired output harmonic is maximized. It is shown that the phase-matching design condition for the single-fed frequency multiplier cannot be used for dual-fed frequency multiplier. Although the phase-matching condition for the dual-feed frequency multiplier can also be used to design the single-feed frequency multiplier, this possibility cannot be recommended for the single-fed configuration as it leads to a longer layout of the circuit.

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Publication Details

Published
2025-03-17
DOI
https://doi.org/10.23919/gemic64734.2025.10979082
Primary Topic
Advanced Power Amplifier Design
Type
article
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On the Phase-Matching Design Condition of Distributed Amplifier Based Frequency Multiplier

Stefan Simion
Advanced Power Amplifier Design
article

On the Phase-Matching Design Condition of Distributed Amplifier Based Frequency Multiplier

Stefan Simion
article en

Abstract

Single- and dual-fed distributed amplifiers based frequency multipliers are analysed for the phase-matching design condition. Based on the nonlinear circuit analysis, phase-matching design conditions are found such that the transistors have an equal contribution to the total output power and also the total output power level on the desired output harmonic is maximized. It is shown that the phase-matching design condition for the single-fed frequency multiplier cannot be used for dual-fed frequency multiplier. Although the phase-matching condition for the dual-feed frequency multiplier can also be used to design the single-feed frequency multiplier, this possibility cannot be recommended for the single-fed configuration as it leads to a longer layout of the circuit.

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