A sub-2 radix split-capacitor DAC for a 12 bit SAR ADC in 28nm CMOS

This work presents the design and optimization of a sub-2 radix split-capacitor digital-to-analog converter (CDAC) utilized in a 333MS/s 12bit successive-approximation-register (SAR) analog-to-digital converter (ADC). Several techniques are proposed, enhancing the DAC settling and linearity performance during the SAR algorithm, including the use of a sub-2 radix redundancy, a split-capacitor CDAC and an extra reference-voltage scaling capacitor to maximize the reference-voltage to 1V, directly reducing the CDAC switch impedance. The benefits and drawbacks of sub-2 radix CDAC realization are highlighted when adopting a 1.81-radix to maintain 12bit settling accuracy with 10% overrange, covering capacitor mismatch and finite settling accuracy. The proposed SAR ADC lane is utilized in a highly time-interleaved (TI) ADC chip manufactured in a standard 28nm CMOS process. The chip is assembled on an interposer and finally packaged for simplified characterization. The SAR ADC achieves an excellent SNDR of 53.5dB and 49dB as well as a spurious free dynamic range (SFDR) of 71dBc and 67dBc for a 1V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</inf> single tone sine wave input signal with a frequency of 90MHz and 4GHz respectively.