Efficient FIR Filter Using Modified Booth Encoding with Wallace Tree

This paper presents an improved and effective multiplier which are crucial components in applications Image processing and Finite Impulse Response Filters. The fundamental operation of arithmetic is multiplication. In comparison to other mathematical operations, multipliers demand greater hardware resources and processing time. Using Modified Booth Encoding and Wallace tree reduction techniques, a low-area, and power-efficient multiplier is developed. The Booth multipliers are operating at a frequency of 250MHz. The Booth multiplier used in FIR filter consumes 17.069W whereas the modified Booth Multiplier consumes 13.169W of power