Multilevel Inverter Using Nearest-Sine-Level Stage-Capacitors with Coupled and Reduced Number of Power Semiconductor Switches

This paper has presented a multilevel inverter (MLI) with reduced number of power semiconductor switches. The MLI is derived from the neutral point clamped (NPC) inverter, where the number of switches at each inverter's upper-part string is reduced and coupled (coupled and reduced number of switches) while still maintaining its performance and functionality. Therefore, the proposed inverter topology is called MLI with coupled and reduced number of switch (CRNS). In order to reduce the total harmonic distortion (THD), the stage-capacitor value for each step/level is set to the nearest-level of sine-wave signal. Compared to a uniform stage-capacitor values (USC) method, the nearest-sine-level stage-capacitor values (NSLSC) show better performance in term of THD and output power. For a 9-level circuit configuration, the THD of the NSLSC method is around 11.97%, and the USC give 14.32% of THD for a certain load setting. The THD can be reduced further by using higher number of levels, with only additional one power switch, one capacitor and one diode for each additional inverter's output level. Another interesting feature of the concept is logic block circuit to implement digital gating signal is also simpler than the conventional method.