Simulation Analysis of TFETs For Low Power And High-Speed Applications

This work presents a simulation study of single and double-gate TFETs to determine the optimal device structure for the potential applications in low-power and fast-switching electronic applications. 2-D Silvaco TCAD tool is used after employing appropriate physical models to analyze the impact of variations in gate work function, intrinsic layer thickness, and gate length on sub-threshold swing (SS) and ION/IOFF. Double-gate TFETs offer enhanced electrostatic control and reduced leakage current over single-gate TFETs. The optimized double-gate device structure with an intrinsic layer thickness of 6 nm, gate length of 160 nm, and gate work function of 4.2 eV resulted in ION/IOFF of 1011 and SS of 30 mV/dec. Moreover, improved scalability and reduced short-channel effects make double-gate TFETs are more suitable for advanced microelectronic devices.