Implementation of Low Power Kogge Stone Adder on Zynq 7000 SoC Evaluation Kit FPGA

Adders are important hardware elements found in most high-speed, digital systems, including FIR filters, digital signal processors, and microprocessors. Digital systems have many different criteria for addition, including those related to size, speed, power consumption, and other factors. While keeping other parameters constant, the adder design focuses decreasing power dissipation. Reducing the dynamic power dissipation is necessary in VLSI design to achieve significant power savings. Selecting a suitable adder that dissipates less power, operates quickly, and is achievable with less cost is the main objective of this process. The goal of this paper is to choose a suitable adder that is affordable, fast, and dissipates less power. In this paper the performance of three 16-bit adders; such as Ripple Carry Adder, Carry Select Adder and Kogge Stone Adder are compared based on on-chip power, latency in datapath and the number of look up tables (LUT)s used by each adder. The design and stimulus blocks of the adders are written in Verilog HDL and simulated in Vivado 2023.1 tool. Furthermore, the adders are implemented on AMD Zynq 7000 SoC ZC702 (ZedBoard) Evaluation Kit FPGA board. Upon execution of the formerly said procedure, it is found that the Kogge stone adder outperforms the other three in terms of on-chip power, delay paths and the LUTs used.