A 4-bit 40 GS/s Power Efficient DAC for 6G Communication Systems

This paper presents a power-efficient 40-GBaud digital-to-analog converter (DAC), with a design approach focused on selecting an optimal bias-current to minimize power consumption while targeting a specific bandwidth. A 4-bit DAC has been fabricated in a 130 nm SiGe BICMOS process and operates at a sampling rate of 40 GS/s. This makes it suitable for high-speed modulation schemes such as 64-QAM and 16-QAM, as well as PAM-8. The circuit has been characterized across a range of supply voltages. With a total power consumption of 76 mW, at a 2.3 V supply voltage, the circuit achieved an energy efficiency of 0.63 pJ/bit; to the best knowledge of the authors, this is the best reported energy efficiency for PAM-8 modulators.