A 21GHz Bandwidth 30dB Gain VGA for 6G Baseband Systems in 22nm FDSOI

This paper presents a 5-stage wideband variable gain amplifier (VGA) integrated in 22nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The circuit comprises three different core circuit topologies composed of an input buffer, three gain control stages, and a high-power output stage. The VGA achieves a 30dB gain with a power consumption of 44mW, exhibiting a continuous tuning range of 33dB, covering a 3dB bandwidth of 21GHz while occupying an area of 0.077mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The VGA is optimized for operation within high-data rate 6G receiver systems.

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Publication Details

Published
2025-03-17
DOI
https://doi.org/10.23919/gemic64734.2025.10979017
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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article

A 21GHz Bandwidth 30dB Gain VGA for 6G Baseband Systems in 22nm FDSOI

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Radio Frequency Integrated Circuit Design
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A 21GHz Bandwidth 30dB Gain VGA for 6G Baseband Systems in 22nm FDSOI

Andre Engelmann, Norman Franchi, Tianzhu Huang, Philip Hetterle, Robert Weigel, Kai Scheller
article en

Abstract

This paper presents a 5-stage wideband variable gain amplifier (VGA) integrated in 22nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The circuit comprises three different core circuit topologies composed of an input buffer, three gain control stages, and a high-power output stage. The VGA achieves a 30dB gain with a power consumption of 44mW, exhibiting a continuous tuning range of 33dB, covering a 3dB bandwidth of 21GHz while occupying an area of 0.077mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The VGA is optimized for operation within high-data rate 6G receiver systems.

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Radio Frequency Integrated Circuit Design
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