Exploring the Wafer-Scale GPUs

Wafer-scale GPU technology has recently been proposed to improve the scalability of multi-GPU systems.By expanding a multi-chiplet module GPU design to the scale of the whole wafer, GPU chiplets can communicate much faster than using off-chip networks.Yet, while the technology is mature in the Electrical Engineering domain, architecture-and system-level research is limited, impeding the deployment of wafer-scale GPUs.In this paper, we perform a series of simulator-based design explorations using three experiments that cover hardware organization, system-level scheduling, and software adaptation.In the hardware organization experiment, we explore how the GPU chiplet size impacts the performance while keeping the wafer size unchanged.The system-level scheduling experiment explores how the performance changes if we change the number of chiplets used, revealing the scalability limitation of current GPU kernels running on wafer-scale GPUs.In the software adaptation experiment, we explore the possibilities of forming pipelines on a wafer to improve performance.Overall, we find that wafer-scale GPUs demonstrate unique properties, and the performance improvement of wafer-scale GPUs cannot rely on solutions established for traditional multi-GPU systems and MCM-GPU devices.