A Highly Integrated 1T CMOS Image Sensor with Enhanced Dynamic Range Performance

Tackling issues of low full well capacity (FWC) and dynamic range (DR) with the process of miniaturization, this paper presents a novel one-transistor (1T) complementary metal- oxide-semiconductor (CMOS) image sensor (CIS) pixel design based on semi-floating gate (SFG) transistor. A backside illumination (BSI), hole-collecting type, 3.1-μm-pitch pixel has been designed. It integrates a vertical photodiode, SFG MOSFET, and deep trench isolation. Key parameters show a remarkable FWC of 105000 h+ and a DR exceeding 94 dB.