Improving Error Resilience in FPGA-Based Multi-Level Approximate Multipliers Using Modified Full Adders

The study provides a novel technique of increasing the tolerance error for FPGAs-dependent multi-level approximate multipliers, in the application of multiplexers along with modified complete adders. Resource usage should be optimized, and circuit simplicity must be improved at last. Although complete adders are critical to the arithmetic operations of digital circuits, the number of adders can increase the amount of power consumed, the amount of space required, and the process time. The proposed design enhances energy efficiency, reduces signal propagation time, and enhances defect tolerance by employing a multiplexer-based adder architecture. The optimized full adder significantly reduces the power consumption up to 27.7%, space utilization up to 22.9%, and gate count up to 22.8% as compared with traditional designs through extensive simulations. The design is suitable for applications that can afford a moderate amount of error as the error rate is less than 5%. This approach provides a long-term, effective, and extensible solution for systems that are constructed using field-programmable gate arrays, all while optimizing power, speed, and dependability for contemporary digital applications.