Design and validation of Mixed Logic 2-to-4 Decoders Using 32nm FinFET Technology

This paper introduces the design and implementation of a 2×4 decoder using FinFET technology at the 32nm process node, leveraging transmission gate logic and dual-value logic to optimize performance. LP (Low power) and LPI(Low power inversion), HP(High Power) and HPI(High Power Inversion) 2×4 decoder is an essential combinational circuit widely used in digital systems for address decoding, de-multiplexing, and control applications. FinFETs offer enhanced electrostatic control and reduced leakage currents, addressing the challenges of traditional MOSFETs at nanoscale dimensions. By incorporating transmission gates, the proposed design minimizes propagation delay and power dissipation, such as 1.06u, static power=101p, dynamic 4.2u and delay offered 560ps achieving high-speed and energy-efficient operation. The use of dual-value logic further reduces the transistor count, leading to a compact layout with optimized area utilization. Simulation results validate the performance of the proposed design, demonstrating significant improvements in power efficiency, delay, and overall reliability compared to conventional CMOS-based decoders. The combination of FinFET technology, transmission gate logic, and dual-value logic highlights a novel approach to designing robust digital circuits in advanced technology nodes.