Design and Analysis of PVT Tolerant and Fast-Settling Wideband CP-PLL Frequency Synthesizer

The design of a fast-settling, PVT-tolerant wideband charge pump-phase locked loop (CP-PLL) frequency synthesizer is introduced in this paper. A differential charge pump utilizing a bootstrapped structure technique is implemented to ensure low phase noise. A differential ring voltage-controlled-oscillator (VCO) is employed, offering a broad tuning range while maintaining excellent phase noise performance. The design also incorporates a programmable divider, adjustable between 16 and 31, at the VCO output to scale down the frequency. The CPPLL synthesizer supports a frequency range of 96 MHz to 5.2 GHz, achieving a locking time of less than 500 ns and a phase alignment error below 100 ps for a 60 MHz reference frequency and a divider value of 28. The entire PLL circuit is realized using SCLPDK 0.18 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu m$</tex> CMOS operation and function at a supply voltage of 1.8 V.