GDI and Dynamic Logic: A Synergy Behind the Modern Electronics

The main goal of this work is to design a 2x2 multiplier as well as a full adder and featuring low power and low delay characteristics, which will be beneficial for creating a low-power arithmetic unit ideal for microprocessors. In order to evaluate the performance parameter, the Cadence Virtuoso software used the Stanford model file for CNTFET at a 32nm technology node. The proposed circuit explored the Dynamic Modified Gate Diffusion Input (DMGDI), a hybrid of Dynamic Logic Block (DLB) and Modified Gate Diffusion Input (MGDI). Since MGDI suffers from ratioed logic and threshold drop, resulting in inadequate swing for certain input combinations. Considering this, the paper proposes the Dynamic Modified Gate Diffusion Input (DMGDI) technique, which integrates DLB with MGDI, resulting in full swing output. The DMGDI-based full adder and 2-bit multiplier are constructed to illustrate the applicability. In comparison to the DGDI (Dynamic Gate Diffusion Input) based full adder and multiplier, the suggested circuitry reduced power consumption by 42.28% and 45.55%, respectively, while also decreasing delay by 30.4% and 42.17%. Thus, the PDP parameter decreased by 59.7% and 68.6% for the proposed DMGDI-based full adders and multipliers, respectively, in comparison to DGDI circuits, indicating the superiority of the recommended circuitry.