Low Power Design Analysis of ALU Using FinFET

This paper aims to provide a comparative analysis of low-power design methods for the implementation of the Arithmetic Logical Unit using Fin- Field Effective Transistor. The study evaluates four new important low-power methodologies: Complementary Metal Oxide Semiconductor, Gate Diffusion Input, Subthreshold and Adiabatic design. The paper aims to be the first of its kind to provide a comparative analysis using these four low-power models in FinFET Technology using the Cadence Virtuoso designing tool. FinFET, being a modern technology with lower power leakage than the conventional MOSFET, is being used in the four design models to test feasibility. These models showcase the practical implications of deploying these sophisticated models in an 8-bit Arithmetic logical unit to harness real-life use cases. The study investigates the tradeoff between the number of transistors required in each design, the power efficiency obtained, the area utilized, the delay, leakage current and the voltage transfer curve. The models are implemented in an ALU to understand how they would perform in real-world computational needs. We were able to obtain a reduction in power consumption of 76% provided by the Subthreshold Adiabatic Logic ALU and a decrease of 83% in the case of GDI based ALU. The findings contribute to understanding how FinFET 7nm technology can optimize power consumption for various digital applications, with potential benefits for both high-performance and low-power domains.