Design and Analysis of 4-bit and 8-bit Vedic Multipliers Using Variable Bit CSLA

A chip comprises many logic blocks and digital circuits, of which multiplier is one of the most common blocks Multipliers are fundamental components in digital circuits, widely used in microprocessors, computers, and image processing. As technology advances, optimizing power, speed, and area is crucial. Vedic Mathematics, known for its efficient computational techniques, provides a powerful approach to multiplier design. This study analyses 4-bit and 8-bit Vedic multipliers using various adders, emphasizing the superiority of the Variable Bit Carry Select Adder (CSLA) over conventional and inexact adders. Vedic multipliers, inspired by ancient mathematical principles, enhance computational efficiency by reducing delay and power consumption. The proposed multiplier achieves a 60% improvement in delay and an 80% reduction in power compared to conventional designs. The variable-bit CSLA optimizes carry propagation, significantly lowering computation time and power consumption while maintaining accuracy. These advancements make the Variable Bit CSLA a strong candidate for high-speed, energy-efficient applications, reinforcing its importance in next-generation digital circuits