Power-Efficient Hybrid-Style Full Adders Utilizing High-Speed Xor-Xnor Circuits

Addition is a basic arithmetic operation and is also a speed-limiting factor in most digital circuits, which can be optimized at different module levels, such as in the case of hybrid logic styles. A hybrid full adder's performance is controlled by the XOR-XNOR circuit for its functionality in terms of different microelectronics circuit factors like power, delays, and driving capacity. In this work, we suggest a redesigned XOR-XNOR circuit to minimize the outputs' delay gap. Moreover, four distinct hybrid logic-based full adders utilizing the altered XOR-XNOR network are suggested. The efficacy of the presented full adders and the enhanced XORXNOR circuit is assessed utilizing 45 nm and 90 nm CMOS designs in Cadence Virtuoso environment. Each proposed circuit offers its own advantages across different parameters. The modified circuit shows an improvement of up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{6 9. 6 \%}$</tex> in power-delay product (PDP) at 90 nm, and when the technology is scaled to 45 nm, an improvement of up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{9 3. 4} \%$</tex> is observed. Compared to existing designs, the proposed full adders show improvements ranging from 1.38% to 53.75% in PDP at 90 nm and from 71.66% to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{9 0. 4 6 \%}$</tex> at 45 nm. To assess the driving capabilities of the proposed full adder, we integrated it into cascaded full adders with 2,4, and 8 -bit configurations. Two of the proposed full adders demonstrate good driving capabilities at higher bit widths. To evaluate the maximum variation, the proposed full adders were also simulated across various process corners.