Power Reduction in NOT, AND and Full Adder Circuits Using Adiabatic Methods

The increasing demand for energy-efficient electronic systems has intensified research into reducing power dissipation in digital logic circuits. This study explores the application of adiabatic logic methods, namely Efficient Charge Recovery Logic (ECRL) and 2N-2N2P, to minimize power consumption. Adiabatic logic employs reversible computing principles to recover energy lost during switching, contrasting traditional CMOS circuits that dissipate energy as heat. This work implements and evaluates inverter, AND gate and full adders using these techniques. Simulations conducted in 45 nm and 180 nm technology nodes highlight significant power savings with adiabatic circuits compared to CMOS counterparts. ECRL demonstrates efficient charge recovery through cross-coupled PMOS and NMOS transistors, while 2N-2N2P offers enhanced energy recovery at lower frequencies. Results indicate a substantial reduction in average power dissipation, with ECRL achieving up to 66.70% power reduction in inverters and 57.33% in AND gates, while 2n-2n2p achieves up to 92% power reduction in AND gates and 37.04% in full adders. These findings affirm the potential of Adiabatic Logic for Energy-Efficient Applications in Portable Devices and sustainable digital systems. This study underscores the viability of these techniques in addressing the growing demand for energy-efficient electronics.