Design and Analysis of a 1-Bit Full Adder Utilizing a Novel Grounded Keeper XOR-XNOR Circuit

Ahstract-A novel hybrid-CMOS logic-style full adder design is presented in this study. To achieve good performance low-energy operations served as the basis for our study into hybrid-CMOS design. Several CMOS logic type circuits are employed in hybrid-CMOS design to create new full adders with the required performance. Both full adders employed in this study, based on a novel 8- T grounded based-keeper XOR-XNOR circuit. The use of a grounded keeper circuit transistor in the proposed study helps prevent charge leakage. Compared to its contemporaries, this circuit output exhibits a power-delay product (PDP) improvement of 35%-55%. Cadence Virtuoso is used to simulate each circuit in the 45nm GPDK CMOS manufacturing technology for transient analysis.