Advanced UART Verification Framework Using UVM and SystemVerilog

Reliable communication is essential to operating 5G-integrated systems such as self-driving vehicles and sophisticated healthcare technologies. UART protocols use UVM for error checking, enabling full-duplex communication with baud rates of up to 128,000 with variable baud rates, as well as user-reconfigurable parameters, including a 58-bit data word, parity checking, and optional stop-bit settings. Verification is executed with Xilinx Vivado for synthesis and deployment operations and simulation by EDA Playground. The solution provides a 28.8% decrease in slice LUT usage, 94% dynamic power efficiency at 1.303W, static power of 0.084W, and a propagation delay of 0.256ns. Optimizations enhance system performance by increasing power efficiency and accuracy. The framework demonstrates exceptional scalability and reusability, which is a vital resource for real-time embedded systems.