Comparative Analysis of Energy-Efficient Approximate Multiplier and Wallace Tree Multiplier for Error-Tolerant Applications

The Wallace tree multiplier is a high-performance digital circuit optimized for efficient binary multiplication. It utilizes a hierarchical structure that reduces the number of adders and minimises critical path delay by summing partial products in a tree-like manner with half-adders and full-adders. Conventional multipliers are confronted with problems associated with high energy consumption and suboptimal area utilization, especially in energy-limited systems. Approximate multipliers can address these issues by balancing computational accuracy with efficiency, making them ideal for error-resilient applications. Two novel compressors architectures are introduced: an 8-transistor and a 14-transistor 4:2 compressor. This approach allows for faster computation compared to conventional array multipliers, making it well-suited for Error-Tolerant applications. The proposed multipliers are designed in Verilog HDL and evaluated through simulation on the Xilinx VIVADO 2018.3 design software, with the Artix-7 AC701 FPGA serving as the target platform. the approximate multiplier uses only 786 transistors, a 49% reduction in size compared to a traditional 1530-transistor Wallace multiplier and significant improvement in area (49 %), power (69.8%) and Accuracy (76%).